Logo des Repositoriums

Auflistung nach Autor:in "Rosenstiel, Wolfgang"

1 - 8 von 8
  • Konferenzbeitrag
    An architecture for runtime evaluation of soc reliability
    (INFORMATIK 2006 – Informatik für Menschen, Band 1, 2006) Bernauer, Andreas; Bringmann, Oliver; Rosenstiel, Wolfgang; Bouajila, Abdelmajid; Stechele, Walter; Herkersdorf, Andreas
    This paper presents an architecture to evaluate the reliability of a systemon-chip (SoC) during its runtime that also accounts for the system's redundancy. We propose to integrate an autonomic layer into the SoC to detect the chip's current condition and instruct appropriate countermeasures. In the autonomic layer, error counters are used to count the number of errors within a fixed time interval. The counters' values accumulate into a global register representing the system's reliability. The accumulation takes into account the series and parallel composition of the system.
  • Zeitschriftenartikel
    DWARF-driven Equivalence Checking of UML Statecharts and Software Components
    (Softwaretechnik-Trends Band 31, Heft 3, 2011) Heckeler, Patrick; Behrend, Jörg; Ruf, Jürgen; Kropf, Thomas; Rosenstiel, Wolfgang; Weiss, Roland
    This article presents an instrumentation-free runtime verification methodology built upon an external observer which uses DWARF1 -statements to monitor system behavior. The observer delivers information about variable values used for state-encoding and method calls representing transitions. These information are passed to an engine which parses the system specification in terms of a UML statechart. It is transformed into an executable automaton which acts as a golden reference for equivalence checking. The presented approach makes it possible to perform verification directly on the target architecture and keeps up test significance by avoiding modification of the executable caused by injected monitors or other code probes
  • Konferenzbeitrag
    Evaluation of the Learning Classifier System XCS for SoC run-time control
    (INFORMATIK 2008. Beherrschbare Systeme - dank Informatik. Band 2, 2008) Bernauer, Andreas; Fritz, Dirk; Rosenstiel, Wolfgang
    In this paper, we evaluate the feasibility of using the learning classifier XCS to control a System-on-Chip. Increasing number of transistors and process variation make it difficult for a chip designer to foresee all possible run-time conditions. Post-poning some decisions from design time to run time alleviates the designer’s life and allows shorter time-to-market. In this paper, we evaluate if XCS can take these run-time decisions on a processor with four cores. The evaluation shows that XCS can find optimal operating points, even in changed environments or with changed reward functions. This even works, though limited, without the genetic algorithm the XCS uses internally. The results motivate us to continue the evaluation for more complex setups.
  • Konferenzbeitrag
    Fast software performance evaluation for embedded hardware in componentbased embedded systems
    (Software-engineering and management 2015, 2015) Pressler, Static Analysismichael; Viehl, Alexander; Bringmann, Oliver; Rosenstiel, Wolfgang
    We present an approach for the extraction of computational demand of embedded software components and the determination of initial mapping configurations on modern embedded heterogeneous processor architectures. The presented work combines the advantages of component-based design and properties obtained from source-code analysis. The goal is a very fast estimation of execution costs for multiple hardware/software component pairs even before the hardware is physically available.
  • Zeitschriftenartikel
    Revitalisierung der akademischen Großrechnerausbildung
    (Informatik-Spektrum: Vol. 34, No. 3, 2011) Spruth, Wilhelm G.; Rosenstiel, Wolfgang
    Großrechner (engl: Mainframe) werden heutzutage gerne als technologische Dinosaurier eingestuft. In Wirklichkeit verfügen sie über eine große Anzahl führender Technologien. Der folgende Aufsatz beschreibt einige Beispiele und schildert unseren Ansatz, dieses Wissen in die akademische Lehre einzubringen.
  • Konferenzbeitrag
    State-based coverage analysis and UML-driven equivalence checking for C++ state machines
    (FM+AM`2010 – Second International Workshop on Formal Methods and Agile Methods, 2010) Heckeler, Patrick; Behrend, Jörg; Kropf, Thomas; Ruf, Jürgen; Rosenstiel, Wolfgang; Weiss, Roland
    This paper presents a methodology using an instrumentation-based behavioral checker to detect behavioral deviations of a C++ object implementing a finite state machine (FSM) and the corresponding specification defined as a UML state chart. The approach is able to link the source code with the appropriate states and provides a coverage analysis to show which states have been covered by unit, system and integration tests. Furthermore, the approach provides statistical information about the distribution of covered lines of code among all included files and directories. As a proof of concept the presented approach has been implemented in terms of a C++-library and has been successfully applied to OPC UA, an industrial automation infrastructure software.
  • Zeitschriftenartikel
    Synthese von Register-Transfer-Strukturen aus Verhaltensbeschriebungen
    (Informatik Spektrum: Vol. 15, No. 1, 1992) Marwedel, Peter; Rosenstiel, Wolfgang
  • Konferenzbeitrag
    Towards a framework and a design methodology for autonomic integrated systems
    (Informatik 2004, Informatik verbindet, Band 2, Beiträge der 34. Jahrestagung der Gesellschaft für Informatik e.V. (GI), 2004) Herkersdorf, Andreas; Rosenstiel, Wolfgang
    The transition from microelectronics to nanoelectronics reaches physical limits and results in a paradigm shift in the design and fabrication of electronic circuits. The conservative worst-case-approach is no longer feasible and has to be replaced by new design methods. These new design methods and tools have to guarantee reliable and robust systems in spite of unsafe and faulty functions on the lowest process levels. This paper proposes autonomic or organic computing principles to be applied to hardware design methods for future SoC solutions. Incorporating self-calibration, fault tolerance or even self-healing concepts into IC systems represents a major conceptual shift which requires new design processes and tools. In the future, guarantee of functional correctness at the chip level will include self-configuration of adaptable components and flexible interfaces supporting a flexible component composition within complex SoC systems. A high quality design process leading to more reliable systems is instrumental to secure a leading position in integrated system design among international competition. Of special interest are typical European application areas like automotive electronics, mobile systems, medical technology, smartcards, etc.