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Optimization potential of CMOS power by wire spacing

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2005

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Gesellschaft für Informatik e.V.

Zusammenfassung

In this work, we identify the power-optimal wire spacing as a geometric program. Its solution is a vector of individual distances between the wires. To quantify the optimization potential by this method we model the output of a grid based router with a set of parallel wires. A comparison of the power values before and after geometric optimization shows that the optimization potential lies well in the two digit percent zone for a representative circuit model in a 130nm process.

Beschreibung

Zuber, Paul; Müller, Florian Helmut; Stechele, Walter (2005): Optimization potential of CMOS power by wire spacing. Informatk 2005. Informatik Live! Band 1. Bonn: Gesellschaft für Informatik e.V.. PISSN: 1617-5468. ISBN: 3-88579-396-2. pp. 344-348. Regular Research Papers. Bonn. 19.-22. September 2005

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