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Architecture-aware cost modelling for parallel performance portability

dc.contributor.authorBelikov, Evgenij
dc.contributor.authorLoidl, Hans-Wolfgang
dc.contributor.authorMichaelson, Greg
dc.contributor.authorTrinder, Phil
dc.contributor.editorJähnichen, Stefan
dc.contributor.editorRumpe, Bernhard
dc.contributor.editorSchlingloff, Holger
dc.date.accessioned2018-11-19T13:30:02Z
dc.date.available2018-11-19T13:30:02Z
dc.date.issued2012
dc.description.abstractLanguages for efficient parallel programming need to achieve high performance portability in order to harness the power offered by rapidly evolving parallel architectures. We use a combination of high-level architecture-aware cost modelling with a low-level, explicit control of coordination as a programming model to improve performance portability. We explore and quantify the impact of heterogeneity in modern parallel architectures on the performance of parallel programs on a range of clusters of multi-cores, varying in architectural parameters such as processor speed, memory size and interconnection speed. Additionally, we develop several formal cost models and automatically use these architectural characteristics to determine suitable granularity and work placement. The effectiveness of such cost-model-driven management of parallelism on common-place cluster hardware is demonstrated by measuring the performance of a parallel sparse matrix multiplication, implemented in C+MPI, on a range of heterogeneous architectures. On a cluster with 16 cores, the speedup increases from 6.2, without any cost model, to 9.1, indicating that even a simple, static cost model is effective in adapting the execution to the target architecture and in significantly improving parallel performance and scalability with negligible overhead.en
dc.identifier.isbn978-3-88579-293-2
dc.identifier.pissn1617-5468
dc.identifier.urihttps://dl.gi.de/handle/20.500.12116/18379
dc.language.isoen
dc.publisherGesellschaft für Informatik e.V.
dc.relation.ispartofSoftware Engineering 2012. Workshopband
dc.relation.ispartofseriesLecture Notes in Informatics (LNI) - Proceedings, Volume P-199
dc.titleArchitecture-aware cost modelling for parallel performance portabilityen
dc.typeText/Conference Paper
gi.citation.endPage120
gi.citation.publisherPlaceBonn
gi.citation.startPage105
gi.conference.date27. Februar - 2. März 2012
gi.conference.locationBerlin
gi.conference.sessiontitleRegular Research Papers

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