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Auflistung nach Autor:in "Bernauer, Andreas"

1 - 2 von 2
  • Konferenzbeitrag
    An architecture for runtime evaluation of soc reliability
    (INFORMATIK 2006 – Informatik für Menschen, Band 1, 2006) Bernauer, Andreas; Bringmann, Oliver; Rosenstiel, Wolfgang; Bouajila, Abdelmajid; Stechele, Walter; Herkersdorf, Andreas
    This paper presents an architecture to evaluate the reliability of a systemon-chip (SoC) during its runtime that also accounts for the system's redundancy. We propose to integrate an autonomic layer into the SoC to detect the chip's current condition and instruct appropriate countermeasures. In the autonomic layer, error counters are used to count the number of errors within a fixed time interval. The counters' values accumulate into a global register representing the system's reliability. The accumulation takes into account the series and parallel composition of the system.
  • Konferenzbeitrag
    Evaluation of the Learning Classifier System XCS for SoC run-time control
    (INFORMATIK 2008. Beherrschbare Systeme - dank Informatik. Band 2, 2008) Bernauer, Andreas; Fritz, Dirk; Rosenstiel, Wolfgang
    In this paper, we evaluate the feasibility of using the learning classifier XCS to control a System-on-Chip. Increasing number of transistors and process variation make it difficult for a chip designer to foresee all possible run-time conditions. Post-poning some decisions from design time to run time alleviates the designer’s life and allows shorter time-to-market. In this paper, we evaluate if XCS can take these run-time decisions on a processor with four cores. The evaluation shows that XCS can find optimal operating points, even in changed environments or with changed reward functions. This even works, though limited, without the genetic algorithm the XCS uses internally. The results motivate us to continue the evaluation for more complex setups.