Logo des Repositoriums

Auflistung nach Autor:in "Buchty, Rainer"

1 - 3 von 3
  • Konferenzbeitrag
    Adaptive Cache Infrastructure: Supporting dynamic Program Changes following dynamic Program Behavior
    (9th workshop on parallel systems and algorithms – workshop of the GI/ITG special interest groups PARS and PARVA, 2008) Nowak, Fabian; Buchty, Rainer; Karl, Wolfgang
    Recent examinations of program behavior at run-time revealed distinct phases. Thus, it is evident that a framework for supporting hardware adaptation to phase behavior is needed. With the memory access behavior being most important and cache accesses being a very big subset of them, we herein propose an infrastructure for fitting cache accesses to a program’s requirements for a distinct phase.
  • Zeitschriftenartikel
    Efficient Synchronization Techniques in a Decentralized Memory Management System Enabling Shared Memory
    (PARS: Parallel-Algorithmen, -Rechnerstrukturen und -Systemsoftware: Vol. 28, No. 1, 2011) Mattes, Oliver; Schindewolf, Martin; Sedler, Roland; Buchty, Rainer; Karl, Wolfgang
    The rising integration level enables combining more logic on a single chip. This is exploited in multiprocessor systems-on-chip (MPSoCs) or manycore research prototypes such as the Intel SCC. These platforms offer access to shared memory over a limited number of controllers which may lead to congestion. In order to scale the memory with the core count, the memory management must become more flexible and distributed in nature. In the near future decentralized systems with multiple selfmanaging memory components will arise. The problem tackled in this paper is how to realize synchronization mechanisms for coincident access to shared memory in such a decentralized memory management system. Furthermore, improvements of the distributed synchronization mechanism are integrated and evaluated. To speed up the synchronization, additional logic in the form of a locks queue, is added. In order to reduce the network traffic this is combined by extending the synchronization protocol with exponential backoff. In the evaluation, side effects of combining both techniques are discussed and explained.
  • Konferenzbeitrag
    Modelling cryptonite on the design of a programmable high-performance crypto processor
    (ARCS 2004 – Organic and pervasive computing, 2004) Buchty, Rainer
    Cryptographic algorithms – even when designed for easy implementability on general purpose architectures – still show a huge performance gap between implementations in software and those using dedicated hardware. Such hardware is usually only able to deal with one single algorithm or a very narrowly defined set of algorithms. The tradeoff between speed/throughput and flexibility can be eased by programmable crypto architectures. These can be existing general purpose architectures enhanced by specialized functional units which fulfill the requirements of typical cryptographic algorithms. Alternatively, a fully custom architecture can be designed. In this paper we describe the methods used to design a programmable crypto architecture from scratch. We will introduce a set of typical cryptographic algorithms, investigate their requirements, and finally show the weighted result leading to our Cryptonite architecture.