Logo des Repositoriums

Auflistung nach Autor:in "Izumi, Shintaro"

1 - 1 von 1
  • Konferenzbeitrag
    Processor coupling architecture for aggressive voltage scaling on multicores
    (ARCS 2012 Workshops, 2012) Kugata, Koji; Soda, Shinpei; Nakata, Yohei; Okumura, Shunsuke; Izumi, Shintaro; Yoshimoto, Masahiko; Kawaguchi, Hiroshi
    We propose novel multicore architecture in which dual processors (positive-true processor element and negativetrue processor element: pPE and nPE) can be combined and serve as a low-voltage/high-performance single PE. The coupling processor occupies a double area, but it operates at a lower voltage or faster than the original processor. The proposed scheme is suitable to voltage scaling on multicores that have abundant PEs. To evaluate and demonstrate the proposed architecture, we designed octa-core coupling DSP in a 65-nm CMOS technology, on which we confirmed a 1-MHz operation at a single supply voltage of 0.5 V.