Auflistung nach Autor:in "Karl, Wolfgang"
1 - 10 von 52
Treffer pro Seite
Sortieroptionen
- KonferenzbeitragAdaptive Cache Infrastructure: Supporting dynamic Program Changes following dynamic Program Behavior(9th workshop on parallel systems and algorithms – workshop of the GI/ITG special interest groups PARS and PARVA, 2008) Nowak, Fabian; Buchty, Rainer; Karl, WolfgangRecent examinations of program behavior at run-time revealed distinct phases. Thus, it is evident that a framework for supporting hardware adaptation to phase behavior is needed. With the memory access behavior being most important and cache accesses being a very big subset of them, we herein propose an infrastructure for fitting cache accesses to a program’s requirements for a distinct phase.
- KonferenzbeitragAdding low-cost hardware barrier support to small commodity clusters(ARCS'06, 19th International Conference on Architecture of Computing Systems, 2006) Hoefler, Torsten; Mehlan, Torsten; Mietke, Frank; Rehm, Wolfgang
- KonferenzbeitragApplications of FPGA reconfiguration for experiments in high energy physics(ARCS'06, 19th International Conference on Architecture of Computing Systems, 2006) Kebschull, Udo
- ZeitschriftenartikelAn Architecture Framework for Porting Applications to FPGAs(PARS-Mitteilungen: Vol. 31, Nr. 1, 2014) Nowak, Fabian; Bromberger, Michael; Karl, WolfgangHigh-level language converters help creating FPGAbased accelerators and allow to rapidly come up with a working prototype. But the generated state machines do often not perform as optimal as hand-designed control units, and they require much area. Also, the created deep pipelines are not very efficient for small amounts of data. Our approach is an architecture framework of hand-coded building blocks (BBs). A microprogrammable control unit allows programming the BBs to perform computations in a data-flow style. We accelerate applications further by executing independent tasks in parallel on different BBs. Our microprogram implementation for the Conjugate-Gradient method on our data-driven, microprogrammable, task-parallel architecture framework on the Convey HC-1 is competitive with a 24-thread Intel Westmere system. It is 1.2× faster using only one out of four available FPGAs, thereby proving its potential for accelerating numerical applications. Moreover, we show that hardware developers can change the BBs and thereby reduce iteration count of a numerical algorithm like the ConjugateGradient method to less than 0.5× due to more precise operations inside the BBs, speeding up execution time 2.47×.
- Editiertes Buch
- KonferenzbeitragAutomated construction of dependability models by aspect-oriented modeling and model transformation(ARCS'06, 19th International Conference on Architecture of Computing Systems, 2006) Domokos, Péter; Majzik, István
- KonferenzbeitragChallenges and trends in the engineering of automotive systems(ARCS'06, 19th International Conference on Architecture of Computing Systems, 2006) Illgen, Thomas; Ortmann, Stefan
- KonferenzbeitragClock frequency variation of partially reconfigurable systems(ARCS'06, 19th International Conference on Architecture of Computing Systems, 2006) Dittmann, Florian; Heimfarth, Tales
- KonferenzbeitragCombitgen: A new approach for creating partial bitstreams in virtex-II pro devices(ARCS'06, 19th International Conference on Architecture of Computing Systems, 2006) Claus, Christopher; Müller, Florian Helmut; Stechele, Walter
- KonferenzbeitragCOMMA: A communications methodology for dynamic module-based reconfiguration of FPGAs(ARCS'06, 19th International Conference on Architecture of Computing Systems, 2006) Koh, Shannon; Diessel, Oliver