Auflistung nach Autor:in "Klassen, Dennis"
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- KonferenzbeitragViCE-UPSLA: A visual high level language for accurate simulation of interlocked pipelined processors(Software Engineering 2013 - Workshopband, 2013) Klassen, DennisSimulation of processors is needed in early stages of development to reduce cost and increase quality of processor designs. Suitable simulators can be generated automatically from high-level specifications of the processor architecture. For this purpose, we have developed the domain specific visual language ViCE-UPSLA. It allows to describe pipeline based register-register, register-memory processor architectures and generates efficient simulators for such processors. In this way a variety of processors can be quickly prototyped for validation and evaluation. We have successfully used ViCE-UPSLA to model and simulate a processor with an ARM [ARM00] like architecture.