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Auflistung nach Autor:in "Ritter, Daniel"

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  • Zeitschriftenartikel
    Comparison of PGAS Languages on a Linked Cell Algorithm
    (PARS-Mitteilungen: Vol. 30, Nr. 1, 2013) Bauer, Martin; Kuschel, Christian; Ritter, Daniel; Sembritzki, Klaus
    The intention of partitioned global address space (PGAS) languages is to decrease developing time of parallel programs by abstracting the view on the memory and communication. Despite the abstraction a decent speed-up is promised. In this paper the performance and implementation time of Co-Array Fortran (CAF)Unified Parallel C (UPC) and Cascade High Productivity Language (Chapel) are compared by means of a linked cell algorithm. An MPI parallel reference implementation in C is ported to CAFChapel and UPCrespectivelyand is optimized with respect to the available features of the corresponding language. Our tests show parallel programs are developed faster with the above mentioned PGAS languages as compared to MPI. We experienced a performance penalty for the PGAS versions that can be reduced at the expense of a similar programming effort as for MPI. Programmers should be aware that the utilization of PGAS languages may lead to higher administrative effort for compiling and executing programs on different super-computers.
  • Zeitschriftenartikel
    Comparison of PGAS Languages on a Linked Cell Algorithm
    (PARS: Parallel-Algorithmen, -Rechnerstrukturen und -Systemsoftware: Vol. 30, No. 1, 2013) Bauer, Martin; Kuschel, Christian; Ritter, Daniel; Sembritzki, Klaus
    The intention of partitioned global address space (PGAS) languages is to decrease developing time of parallel programs by abstracting the view on the memory and communication. Despite the abstraction a decent speed-up is promised. In this paper the performance and implementation time of Co-Array Fortran (CAF), Unified Parallel C (UPC) and Cascade High Productivity Language (Chapel) are compared by means of a linked cell algorithm. An MPI parallel reference implementation in C is ported to CAF, Chapel and UPC, respectively, and is optimized with respect to the available features of the corresponding language. Our tests show parallel programs are developed faster with the above mentioned PGAS languages as compared to MPI. We experienced a performance penalty for the PGAS versions that can be reduced at the expense of a similar programming effort as for MPI. Programmers should be aware that the utilization of PGAS languages may lead to higher administrative effort for compiling and executing programs on different super-computers.
  • Textdokument
    Exploring Memory Access Patterns for Graph Processing Accelerators
    (BTW 2021, 2021) Dann, Jonas; Ritter, Daniel; Fröning, Holger
    Recent trends in business and technology (e.g., machine learning, social network analysis) benefit from storing and processing growing amounts of graph-structured data in databases and data science platforms. FPGAs as accelerators for graph processing with a customizable memory hierarchy promise solving performance problems caused by inherent irregular memory access patterns on traditional hardware (e.g., CPU). However, developing such hardware accelerators is yet time-consuming and difficult and benchmarking is non-standardized, hindering comprehension of the impact of memory access pattern changes and systematic engineering of graph processing accelerators. In this work, we propose a simulation environment for the analysis of graph processing accelerators based on simulating their memory access patterns. Further, we evaluate our approach on two state-of-the-art FPGA graph processing accelerators and show reproducibility, comparablity, as well as the shortened development process by an example. Not implementing the cycle-accurate internal data flow on accelerator hardware like FPGAs significantly reduces the implementation time, increases the benchmark parameter transparency, and allows comparison of graph processing approaches.
  • Konferenzbeitrag
    Working with Disaggregated Systems. What are the Challenges and Opportunities of RDMA and CXL?
    (BTW 2023, 2023) Geyer, Andreas; Ritter, Daniel; Lee, Dong Hun; Ahn, Minseon; Pietrzyk, Johannes; Krause, Alexander; Habich, Dirk; Lehner, Wolfgang
    The usage of disaggregated systems in large scale data-centers offers a lot of flexibility and easy scalability in comparison to the traditional statically configured scale-up and scaleout systems. Disaggregated architectures allow for the creation of software composable systems in order to create a virtual machine by software out of the pool of available hardware resources. In this paper, we propose a memory disaggregation classification and applicable use cases. We would be delighted to present our ideas and the memory disaggregation classification at the workshop and discuss the presented ideas. The valuable feedback of the attendees will help us to further refine our classification both in terms of preciseness and applicability.