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Auflistung nach Autor:in "Schnor, Bettina"

1 - 5 von 5
  • Konferenzbeitrag
    Automated Detection of Bugs in Error Handling for Teaching Secure C Programming
    (Proceedings of the Sixth Workshop "Automatische Bewertung von Programmieraufgaben" (ABP 2023), 2023) Schrötter, Max; Falk, Maximilian; Schnor, Bettina
    The Low-Level programming language C is widely used for Operating Systems, Embedded Systems and other performance critical applications. Since these applications are often security critical, they require secure programming. The C language on the other hand allows novice programmers to write insecure code easily. This makes it especially important to teach secure programming and give students feedback on potential security issues. One critical bug that is often overlooked is the incorrect handling of errors. In this paper, we present an Error Handling Analyzer (EHA) for the CoFee framework. The EHA detects missing error handling and incorrect error handling using the Clang Static Analyzer. We evaluated EHA on 100 student submissions and found that error handling bugs are a common mistake and that EHA can detect more than 80 % of the error handling bugs in these submissions.
  • Zeitschriftenartikel
    Comparing MPI Passive Target Synchronization Schemes on a Non-Cache-Coherent Shared-Memory Processor
    (PARS-Mitteilungen: Vol. 35, Nr. 1, 2020) Christgau, Steffen; Schnor, Bettina
    MPI passive target synchronisation offers exclusive and shared locks. These are the building blocks for the implementation of applications with Readers & Writers semantic, like for example distributed hash tables. This paper discusses the implementation of MPI passive target synchronisation on a non-cache-coherent multicore, the Intel Single-Chip Cloud Computer. The considered algorithms differ in their communication style, their data structures, and their semantics. It is shown that shared memory approaches scale very well and deliver good performance, even in absence of cache coherence.
  • Zeitschriftenartikel
    A comparison of CUDA and OpenACC: Accelerating the Tsunami Simulation EasyWave
    (PARS-Mitteilungen: Vol. 31, Nr. 1, 2014) Christgau, Steffen; Spazier, Johannes; Schnor, Bettina; Hammitzsch, Martin; Babeyko, Andrey; Wächter, Joachim
    This paper presents an GPU accelerated version of the tsunami simulation EasyWave. Using two different GPU generations (Nvidia Tesla and Fermi) different optimization techniques were applied to the application following the principle of locality. Their performance impact was analyzed for both hardware generations. The Fermi GPU not only has more cores, but also possesses a L2 cache shared by all streaming multiprocessors. It is revealed that even the most tuned code on the Tesla does not reach the performance of the unoptimized code on the Fermi GPU. Further, a comparison between CUDA and OpenACC shows that the platform independent approach does not reach the speed of the native CUDA code. A deeper analysis shows that memory access patterns have a critical impact on the compute kernels’ performance, although this seems to be caused by the compiler in use.
  • Zeitschriftenartikel
    Design of MPI Passive Target Synchronization for a Non-Cache-Coherent Many-Core Processor
    (PARS-Mitteilungen: Vol. 34, Nr. 1, 2017) Christgau, Steffen; Schnor, Bettina
    Distributed hash tables are a common approach for fast data access. For this kind of application, a synchronization scheme with Readers and Writers semantic is well suited. This paper presents the design of an implementation of MPI passive target synchronization with Readers and Writers semantic. The implementation is discussed for the Single-Chip Cloud Computer, a non-cachecoherent many-core CPU with shared memory.
  • Zeitschriftenartikel
    Synchronization of MPI One-Sided Communication on a Non-Cache-Coherent Many-Core System
    (PARS-Mitteilungen: Vol. 33, Nr. 1, 2016) Christgau, Steffen; Schnor, Bettina
    This paper discusses the design and implementation of MPI’s general active target synchronization on the Intel Single-Chip Cloud Computer, a non-cache-coherent many-core CPU. Measurements show a performance benefit of a factor of four compared to the default SCC-tuned MPI implementation and demonstrate the feasibility of implementing efficiently a shared memory protocol despite the lack of cache coherence. Further, a classification of implementation designs of MPI’s general active target synchronization is presented.