Logo des Repositoriums

Auflistung nach Schlagwort "Memory Access"

1 - 2 von 2
  • Zeitschriftenartikel
    Efficient Synchronization Techniques in a Decentralized Memory Management System Enabling Shared Memory
    (PARS: Parallel-Algorithmen, -Rechnerstrukturen und -Systemsoftware: Vol. 28, No. 1, 2011) Mattes, Oliver; Schindewolf, Martin; Sedler, Roland; Buchty, Rainer; Karl, Wolfgang
    The rising integration level enables combining more logic on a single chip. This is exploited in multiprocessor systems-on-chip (MPSoCs) or manycore research prototypes such as the Intel SCC. These platforms offer access to shared memory over a limited number of controllers which may lead to congestion. In order to scale the memory with the core count, the memory management must become more flexible and distributed in nature. In the near future decentralized systems with multiple selfmanaging memory components will arise. The problem tackled in this paper is how to realize synchronization mechanisms for coincident access to shared memory in such a decentralized memory management system. Furthermore, improvements of the distributed synchronization mechanism are integrated and evaluated. To speed up the synchronization, additional logic in the form of a locks queue, is added. In order to reduce the network traffic this is combined by extending the synchronization protocol with exponential backoff. In the evaluation, side effects of combining both techniques are discussed and explained.
  • Zeitschriftenartikel
    Is There Hope for Automatic Parallelization of Legacy Industry Automation Applications?
    (PARS: Parallel-Algorithmen, -Rechnerstrukturen und -Systemsoftware: Vol. 28, No. 1, 2011) Kempf, Stefan; Veldema, Ronald; Philippsen, Michael
    Multicore processors have become common in desktop workstations. The trend towards multicores extends to consumer embedded systems like smartphones. In the future, systems for industry automation will also use multiprocessors. In order to migrate legacy industry automation codes to the new hardware platforms, they must be parallelized. As manual parallelization is known to be error-prone, an automatic parallelization is desirable. We investigate how well legacy applications are suited to an automatic parallelization at the function level. We use compiler analyses to determine the amount of parallelism in the program and calculate the potential speedup. We analyze a total of 44 factory control programs to understand how well real codes can be parallelized and show that 13 codes can be parallelized with a reasonable speedup.