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dc.contributor.authorKlassen, Dennis
dc.contributor.editorWagner, Stefan
dc.contributor.editorLichter, Horst
dc.date.accessioned2018-10-24T10:00:37Z
dc.date.available2018-10-24T10:00:37Z
dc.date.issued2013
dc.identifier.isbn978-3-88579-609-1
dc.identifier.issn1617-5468
dc.identifier.urihttp://dl.gi.de/handle/20.500.12116/17415
dc.description.abstractSimulation of processors is needed in early stages of development to reduce cost and increase quality of processor designs. Suitable simulators can be generated automatically from high-level specifications of the processor architecture. For this purpose, we have developed the domain specific visual language ViCE-UPSLA. It allows to describe pipeline based register-register, register-memory processor architectures and generates efficient simulators for such processors. In this way a variety of processors can be quickly prototyped for validation and evaluation. We have successfully used ViCE-UPSLA to model and simulate a processor with an ARM [ARM00] like architecture.en
dc.language.isoen
dc.publisherGesellschaft für Informatik e.V.
dc.relation.ispartofSoftware Engineering 2013 - Workshopband
dc.relation.ispartofseriesLecture Notes in Informatics (LNI) - Proceedings, Volume P-215
dc.titleViCE-UPSLA: A visual high level language for accurate simulation of interlocked pipelined processorsen
dc.typeText/Conference Paper
dc.pubPlaceBonn
mci.reference.pages59-74
mci.conference.sessiontitleRegular Research Papers
mci.conference.locationAachen
mci.conference.date26. Februar-1. März 2013


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