Now showing items 1-4 of 4
Synchronization of MPI One-Sided Communication on a Non-Cache-Coherent Many-Core System
PARS-Mitteilungen: Vol. 33, Nr. 1; 12. PASA-Workshop 2016
This paper discusses the design and implementation of MPI’s general active target synchronization on the Intel Single-Chip Cloud Computer, a non-cache-coherent many-core CPU. Measurements show a performance benefit of a factor of four compared to the default SCC-tuned MPI implementation and demonstrate the feasibility ...
A comparison of CUDA and OpenACC: Accelerating the Tsunami Simulation EasyWave
PARS-Mitteilungen: Vol. 31, Nr. 1
This paper presents an GPU accelerated version of the tsunami simulation EasyWave. Using two different GPU generations (Nvidia Tesla and Fermi) different optimization techniques were applied to the application following the principle of locality. Their performance impact was analyzed for both hardware generations. The ...
Design of MPI Passive Target Synchronization for a Non-Cache-Coherent Many-Core Processor
PARS-Mitteilungen: Vol. 34, Nr. 1
Distributed hash tables are a common approach for fast data access. For this kind of application, a synchronization scheme with Readers and Writers semantic is well suited. This paper presents the design of an implementation of MPI passive target synchronization with Readers and Writers semantic. The implementation is ...
Comparing MPI Passive Target Synchronization Schemes on a Non-Cache-Coherent Shared-Memory Processor
PARS-Mitteilungen: Vol. 35, Nr. 1
MPI passive target synchronisation offers exclusive and shared locks. These are the building blocks for the implementation of applications with Readers & Writers semantic, like for example distributed hash tables. This paper discusses the implementation of MPI passive target synchronisation on a non-cache-coherent ...