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Novel Image Processing Architecture for 3D Integrated Circuits

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2015

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Gesellschaft für Informatik e.V., Fachgruppe PARS

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Utilizing highly parallel processors for high speed embedded image processing is a well known approach. However, the question of how to provide a sufficiently fast data rate from image sensor to processing unit is still not solved. As Trough-Silicon-Vias (TSV), a new technology for chip stacking, become available, parallel image transmission from the image sensor to processing unit is enabled. Nevertheless, the usage of a new technology requires architectural changes in the processing units. With this technology at hand, we present a novel image preprocessing architecture suitable for image processing in 3D chips stacks. The architecture was developed in parallel with a customized image sensor to make a real assembly possible. It is fully functionally verified and layouted for a 150 nm process. Our performance estimation shows a processing speed of 770 up to 14.400 fps (frames per second) for 5 × 5 filters.

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Pfundt, Benjamin; Reichenbach, Marc; Söll, Christopher; Fey, Dietmar (2015): Novel Image Processing Architecture for 3D Integrated Circuits. PARS-Mitteilungen: Vol. 32, Nr. 1. Berlin: Gesellschaft für Informatik e.V., Fachgruppe PARS. PISSN: 0177-0454

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