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dc.contributor.authorZeppenfeld, J.
dc.contributor.authorBouajila, A.
dc.contributor.authorStechele, W.
dc.contributor.authorHerkersdorf, A.
dc.contributor.editorHegering, Heinz-Gerd
dc.contributor.editorLehmann, Axel
dc.contributor.editorOhlbach, Hans Jürgen
dc.contributor.editorScheideler, Christian
dc.date.accessioned2019-04-03T12:45:23Z
dc.date.available2019-04-03T12:45:23Z
dc.date.issued2008
dc.identifier.isbn978-3-88579-228-4
dc.identifier.issn1617-5468
dc.identifier.urihttp://dl.gi.de/handle/20.500.12116/21283
dc.description.abstractThis paper introduces a new hardware-based machine learning building block – called Learning Classifier Table (LCT) – for the run-time reliability, performance and power optimization of future generations of Systems-on-Chip. LCT inherits concepts from the reinforcement learning techniques found in Learning Classifier Systems. Prediction weighted LCT rule evaluation is implemented on a clock cycle scale with low hardware complexity.en
dc.language.isoen
dc.publisherGesellschaft für Informatik e. V.
dc.relation.ispartofINFORMATIK 2008. Beherrschbare Systeme - dank Informatik. Band 2
dc.relation.ispartofseriesLecture Notes in Informatics (LNI) - Proceedings, Volume P-134
dc.titleLearning Classifier Tables for Autonomic Systems on Chipen
dc.typeText/Conference Paper
dc.pubPlaceBonn
mci.reference.pages771-778
mci.conference.sessiontitleRegular Research Papers
mci.conference.locationMünchen
mci.conference.date8.-13. September 2008


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