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dc.contributor.authorJanßen, Benedikt
dc.contributor.authorWingender, Tim
dc.contributor.authorHübner, Michael
dc.contributor.editorEibl, Maximilian
dc.contributor.editorGaedke, Martin
dc.date.accessioned2017-08-28T23:48:34Z
dc.date.available2017-08-28T23:48:34Z
dc.date.issued2017
dc.identifier.isbn978-3-88579-669-5
dc.identifier.issn1617-5468
dc.description.abstractReconfigurable System-on-Chips (SoC) combine processor cores with Field-Programmable Gate Array (FPGA) fabric. Thereby, these systems enable to optimize the execution of application to some extend by hardware accelerators in the FPGA fabric. However, hardware accelerator development requires special skills from the developer since hardware development differs substantial from software development. Overlays offer a way to abstract the complexity of FPGA usage by predefined programmable hardware architectures. With Dynamic Partial reconfiguration (DPR) it becomes possible to exchange parts of an overlay’s architecture without affecting the operation of the remaining parts. In this article, we present a first version of our framework to ease the integration of hardware accelerators in Python via DPR overlays. The integration into Python is based on Xilinx PYNQ. The framework approach is based on our Python package ‘pynqpartial’.en
dc.language.isoen
dc.publisherGesellschaft für Informatik, Bonn
dc.relation.ispartofINFORMATIK 2017
dc.relation.ispartofseriesLecture Notes in Informatics (LNI) - Proceedings, Volume P-275
dc.subjectHardware Accelerator
dc.subjectFPGA
dc.subjectPython
dc.subjectPYNQ
dc.titleHardware Accelerator Framework Approach for Dynamic Partial Reconfigurable Overlays on Xilinx PYNQen
mci.reference.pages481-492
mci.conference.sessiontitleHardware Defined Programming
mci.conference.locationChemnitz
mci.conference.date25.-29. September 2017
dc.identifier.doi10.18420/in2017_44


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