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Resilient data encoding for fault-prone signal transmission in parallelized signed-digit based arithmetic

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dc.contributor.authorNeuhäuser, David
dc.contributor.authorZehendner, Eberhard
dc.date.accessioned2017-12-06T09:10:06Z
dc.date.available2017-12-06T09:10:06Z
dc.date.issued2012
dc.description.abstractWhen arithmetic components are parallelized, fault-prone interconnections can tamper results significantly. Constantly progressing technology scaling leads to a steady increase of errors caused by faulty transmission. Resilient data encoding schemes can be used to offset these negative effects. Focusing on parallel signed-digit based arithmetic frequently used in high-speed systems, we propose suitable data encodings that reduce error rates by 25%. Data encoding should be driven by the occurrence probabilities of digits. We develop a methodology to obtain these probabilities, show an example fault-tolerant encoding, and discuss its impact on communicating parallel arithmetic circuits in an example error scenario.en
dc.identifier.doi10.1007/BF03342021
dc.identifier.pissn0177-0454
dc.identifier.urihttps://dl.gi.de/handle/20.500.12116/8617
dc.language.isoen
dc.publisherGesellschaft für Informatik e.V.
dc.relation.ispartofPARS: Parallel-Algorithmen, -Rechnerstrukturen und -Systemsoftware: Vol. 29, No. 1
dc.relation.ispartofseriesPARS: Parallel-Algorithmen, -Rechnerstrukturen und -Systemsoftware
dc.subjectReduce Error Rate
dc.subjectDigit Error
dc.subjectDigit Probability
dc.subjectError Scenario
dc.subjectRedundant Encode
dc.titleResilient data encoding for fault-prone signal transmission in parallelized signed-digit based arithmeticen
dc.typeText/Journal Article
gi.citation.endPage14
gi.citation.startPage5

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