Proximity Scheme for Instruction Caches in Tiled CMP Architectures
| dc.contributor.author | Alawneh, Tareq | |
| dc.contributor.author | Chi, Chi Ching | |
| dc.contributor.author | Elhossini, Ahmed | |
| dc.contributor.author | Juurlink, Ben | |
| dc.date.accessioned | 2017-06-29T14:30:51Z | |
| dc.date.available | 2017-06-29T14:30:51Z | |
| dc.date.issued | 2015 | |
| dc.description.abstract | Recent research results show that there is a high degree of code sharing between cores in multi-core architectures. In this paper we propose a proximity scheme for the instruction caches, a scheme in which the shared code blocks among the neighbouring L2 caches in tiled multi-core architectures are exploited to reduce the average cache miss penalty and the on-chip network traffic. We evaluate the proposed proximity scheme for instruction caches using a full-system simulator running an n-core tiled CMP. The experimental results reveal a significant execution time improvement of up to 91.4% for microbenchmarks whose instruction footprint does not fit in the private L2 cache. For real applications from the PARSEC benchmarks suite, the proposed scheme results in speedups of up to 8%. | en |
| dc.identifier.pissn | 0177-0454 | |
| dc.language.iso | en | |
| dc.publisher | Gesellschaft für Informatik e.V., Fachgruppe PARS | |
| dc.relation.ispartof | PARS-Mitteilungen: Vol. 32, Nr. 1 | |
| dc.title | Proximity Scheme for Instruction Caches in Tiled CMP Architectures | en |
| dc.type | Text/Journal Article | |
| gi.citation.publisherPlace | Berlin |
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