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Towards a Flexible Fault-Tolerant System-on-Chip

dc.contributor.authorAlbrecht, C.
dc.contributor.authorKoch, R.
dc.contributor.authorPionteck, T.
dc.contributor.authorGlösekötter, P.
dc.date.accessioned2017-12-06T08:58:49Z
dc.date.available2017-12-06T08:58:49Z
dc.date.issued2010
dc.description.abstractC. Albrecht, R. Koch, T. Piontecken
dc.identifier.doi10.1007/BF03345439
dc.identifier.pissn0724-5319
dc.identifier.urihttps://dl.gi.de/handle/20.500.12116/8529
dc.language.isoen
dc.publisherGesellschaft für Informatik e.V.
dc.relation.ispartofFERS-Mitteilungen: Vol. 28, No. 1
dc.relation.ispartofseriesFERS-Mitteilungen
dc.subjectCombinational Logic
dc.subjectMemory Element
dc.subjectSoft Error
dc.subjectTransient Fault
dc.subjectArchitectural Layer
dc.titleTowards a Flexible Fault-Tolerant System-on-Chipen
dc.typeText/Journal Article
gi.citation.endPage27
gi.citation.startPage20

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