SDVMR: A Scalable Firmware for FPGA-based Multi-Core Systems-on-Chip
| dc.contributor.author | Hofmann, Andreas | |
| dc.contributor.author | Waldschmidt, Klaus | |
| dc.contributor.editor | Nagel, Wolfgang E. | |
| dc.contributor.editor | Hoffmann, Rolf | |
| dc.contributor.editor | Koch, Andreas | |
| dc.date.accessioned | 2019-05-06T10:35:47Z | |
| dc.date.available | 2019-05-06T10:35:47Z | |
| dc.date.issued | 2008 | |
| dc.description.abstract | As the main scope of mobile embedded systems shifts from control to data processing tasks high performance demand and limited energy budgets are often seen conflicting design goals. Heterogeneous, adaptive multicore systems are one approach to meet these challenges. Thus, the importance of multicore FPGAs as an implementation platform steadily grows. However, efficient exploitation of parallelism and dynamic runtime reconfiguration poses new challenges for application software developement. In this paper the implementation of a virtualization layer between applica- tions and the multicore FPGA is described. This virtualization allows a transparent runtime-reconfiguration of the underlying system for adaption to changing system environments. The parallel application does not see the underlying, even heterogeneous multicore system. Many of the requirements for an adaptive FPGA-realization are met by the SDVM, the scalable dataflow-driven virtual machine. This paper describes the concept of the FPGA firmware based on a reimplementation and adaptation of the SDVM. | en |
| dc.identifier.isbn | 978-3-88579-218-5 | |
| dc.identifier.pissn | 1617-5468 | |
| dc.identifier.uri | https://dl.gi.de/handle/20.500.12116/22275 | |
| dc.language.iso | en | |
| dc.publisher | Gesellschaft für Informatik e. V. | |
| dc.relation.ispartof | 9th workshop on parallel systems and algorithms – workshop of the GI/ITG special interest groups PARS and PARVA | |
| dc.relation.ispartofseries | Lecture Notes in Informatics (LNI) - Proceedings, Volume P-124 | |
| dc.title | SDVMR: A Scalable Firmware for FPGA-based Multi-Core Systems-on-Chip | en |
| dc.type | Text/Conference Paper | |
| gi.citation.endPage | 58 | |
| gi.citation.publisherPlace | Bonn | |
| gi.citation.startPage | 49 | |
| gi.conference.date | February 26th, 2008 | |
| gi.conference.location | Dresden | |
| gi.conference.sessiontitle | Regular Research Papers |
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