ViCE-UPSLA: A visual high level language for accurate simulation of interlocked pipelined processors
| dc.contributor.author | Klassen, Dennis | |
| dc.contributor.editor | Wagner, Stefan | |
| dc.contributor.editor | Lichter, Horst | |
| dc.date.accessioned | 2018-10-24T10:00:37Z | |
| dc.date.available | 2018-10-24T10:00:37Z | |
| dc.date.issued | 2013 | |
| dc.description.abstract | Simulation of processors is needed in early stages of development to reduce cost and increase quality of processor designs. Suitable simulators can be generated automatically from high-level specifications of the processor architecture. For this purpose, we have developed the domain specific visual language ViCE-UPSLA. It allows to describe pipeline based register-register, register-memory processor architectures and generates efficient simulators for such processors. In this way a variety of processors can be quickly prototyped for validation and evaluation. We have successfully used ViCE-UPSLA to model and simulate a processor with an ARM [ARM00] like architecture. | en |
| dc.identifier.isbn | 978-3-88579-609-1 | |
| dc.identifier.pissn | 1617-5468 | |
| dc.identifier.uri | https://dl.gi.de/handle/20.500.12116/17415 | |
| dc.language.iso | en | |
| dc.publisher | Gesellschaft für Informatik e.V. | |
| dc.relation.ispartof | Software Engineering 2013 - Workshopband | |
| dc.relation.ispartofseries | Lecture Notes in Informatics (LNI) - Proceedings, Volume P-215 | |
| dc.title | ViCE-UPSLA: A visual high level language for accurate simulation of interlocked pipelined processors | en |
| dc.type | Text/Conference Paper | |
| gi.citation.endPage | 74 | |
| gi.citation.publisherPlace | Bonn | |
| gi.citation.startPage | 59 | |
| gi.conference.date | 26. Februar-1. März 2013 | |
| gi.conference.location | Aachen | |
| gi.conference.sessiontitle | Regular Research Papers |
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