Novel Image Processing Architecture for 3D Integrated Circuits
| dc.contributor.author | Pfundt, Benjamin | |
| dc.contributor.author | Reichenbach, Marc | |
| dc.contributor.author | Söll, Christopher | |
| dc.contributor.author | Fey, Dietmar | |
| dc.date.accessioned | 2017-06-29T14:30:50Z | |
| dc.date.available | 2017-06-29T14:30:50Z | |
| dc.date.issued | 2015 | |
| dc.description.abstract | Utilizing highly parallel processors for high speed embedded image processing is a well known approach. However, the question of how to provide a sufficiently fast data rate from image sensor to processing unit is still not solved. As Trough-Silicon-Vias (TSV), a new technology for chip stacking, become available, parallel image transmission from the image sensor to processing unit is enabled. Nevertheless, the usage of a new technology requires architectural changes in the processing units. With this technology at hand, we present a novel image preprocessing architecture suitable for image processing in 3D chips stacks. The architecture was developed in parallel with a customized image sensor to make a real assembly possible. It is fully functionally verified and layouted for a 150 nm process. Our performance estimation shows a processing speed of 770 up to 14.400 fps (frames per second) for 5 × 5 filters. | en |
| dc.identifier.pissn | 0177-0454 | |
| dc.language.iso | en | |
| dc.publisher | Gesellschaft für Informatik e.V., Fachgruppe PARS | |
| dc.relation.ispartof | PARS-Mitteilungen: Vol. 32, Nr. 1 | |
| dc.title | Novel Image Processing Architecture for 3D Integrated Circuits | en |
| dc.type | Text/Journal Article | |
| gi.citation.publisherPlace | Berlin |
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