Impact of sneak paths on in-memory logic design in memristive crossbars
| dc.contributor.author | Datta, Kamalika | |
| dc.contributor.author | Deb, Arighna | |
| dc.contributor.author | Kole, Abhoy | |
| dc.contributor.author | Drechsler, Rolf | |
| dc.date.accessioned | 2023-06-06T10:40:13Z | |
| dc.date.available | 2023-06-06T10:40:13Z | |
| dc.date.issued | 2023 | |
| dc.description.abstract | Resistive Random Access Memory (RRAM), also termed as memristors, is a non-volatile memory where information is stored in memory cells in the form of resistance. Due to its non-volatile resistive switching properties, memristors, in the form of crossbars, are used for storing information, neuromorpic computing, and logic synthesis. In spite of the wide range of applications, memristive crossbars suffer from a so-called sneak path problem which results in an erroneous reading of memristor’s state. Till date, no or very few logic synthesis approaches for in-memory computing have considered the sneak path problem during the realizations of Boolean functions. In other words, the effects of sneak paths on the Boolean function realizations in crossbars still remain an open problem. In this paper, we have addressed this issue. In particular, we study the impacts of function realizations in two memristive crossbar structures: Zero-Transistor-One-Resistor (0T1R) and One-Transistor-One-Resistor (1T1R) in the presence of sneak paths. Experimental analysis on IWLS and ISCAS-85 benchmarks shows that even in the presence of sneak paths, the 1T1R crossbar structures with multiple rows and columns are the most efficient as compared to the 1T1R structures with single row and multiple columns in terms of crossbar size and number of execution cycles. | en |
| dc.identifier.doi | 10.1515/itit-2023-0020 | |
| dc.identifier.pissn | 2196-7032 | |
| dc.identifier.uri | https://dl.gi.de/handle/20.500.12116/41703 | |
| dc.language.iso | en | |
| dc.publisher | De Gruyter | |
| dc.relation.ispartof | it - Information Technology: Vol. 65, No. 1-2 | |
| dc.subject | logic-in-memory; memristor crossbar; RRAM; sneak path | |
| dc.title | Impact of sneak paths on in-memory logic design in memristive crossbars | en |
| dc.type | Text/Journal Article | |
| gi.citation.endPage | 39 | |
| gi.citation.publisherPlace | Berlin | |
| gi.citation.startPage | 29 | |
| gi.conference.sessiontitle | Article |