Optimizing multi-level ReRAM memory for low latency and low energy consumption
| dc.contributor.author | Hosseinzadeh, Shima | |
| dc.contributor.author | Klemm, Marius | |
| dc.contributor.author | Fischer, Georg | |
| dc.contributor.author | Fey, Dietmar | |
| dc.date.accessioned | 2023-06-06T10:40:13Z | |
| dc.date.available | 2023-06-06T10:40:13Z | |
| dc.date.issued | 2023 | |
| dc.description.abstract | With decreasing die size and the ability to store multiple bits in a single cell, resistive random access memory (ReRAM) can be used to increase storage density, making it a promising technology for the next generation of memory. However, multi-level write operations suffer from impairments such as large latency, high energy consumption, and reliability issues. In this paper, we study different mechanisms affecting the “multi-level incremental step pulse with verify algorithm” (M-ISPVA) on a 1-transistor-1-resistor (1T1R) model in transient simulation at the component and the circuit level with focus on resistance control and energy consumption during the entire process of state transitions. By dividing the M-ISPVA into a triggering and a controlling period, we discovered the transistor to operate in the ohmic region during the triggering period as a voltage-controlled resistance and in the saturation region during the controlling period as a voltage-controlled current limiter. Controlling the gate voltage in the triggering period can move the triggering point to a desired write voltage and in the controlling period can increase or decrease resistance steps per pulse to attain a desired speed of resistance change. In addition, the major energy portion is consumed for reset operation during triggering and for set operation during the controlling period. To optimize write performance, extra precaution must be taken when defining resistance states with target read-out current and gate voltage with the focus on evenly balanced latencies between all transitions. A direct multi-level write operation shows 67.5 % latency and 62.5 % energy saving compared to indirect ones, but suffers from only unidirectional control, making it non-feasible. In case of a 4 k bit memory, the more reliable M-ISPVA faces almost 37 % higher latency and energy compared to the basic ISPVA. | en |
| dc.identifier.doi | 10.1515/itit-2023-0022 | |
| dc.identifier.pissn | 2196-7032 | |
| dc.identifier.uri | https://dl.gi.de/handle/20.500.12116/41705 | |
| dc.language.iso | en | |
| dc.publisher | De Gruyter | |
| dc.relation.ispartof | it - Information Technology: Vol. 65, No. 1-2 | |
| dc.subject | 1T1R; ISPVA; M-ISPVA; MLC; non-volatile memory; ReRAM; ternary memory model; write-verification | |
| dc.title | Optimizing multi-level ReRAM memory for low latency and low energy consumption | en |
| dc.type | Text/Journal Article | |
| gi.citation.endPage | 64 | |
| gi.citation.publisherPlace | Berlin | |
| gi.citation.startPage | 52 | |
| gi.conference.sessiontitle | Article |