Exploring Memory Access Patterns for Graph Processing Accelerators
| dc.contributor.author | Dann, Jonas | |
| dc.contributor.author | Ritter, Daniel | |
| dc.contributor.author | Fröning, Holger | |
| dc.contributor.editor | Kai-Uwe Sattler | |
| dc.contributor.editor | Melanie Herschel | |
| dc.contributor.editor | Wolfgang Lehner | |
| dc.date.accessioned | 2021-03-16T07:57:12Z | |
| dc.date.available | 2021-03-16T07:57:12Z | |
| dc.date.issued | 2021 | |
| dc.description.abstract | Recent trends in business and technology (e.g., machine learning, social network analysis) benefit from storing and processing growing amounts of graph-structured data in databases and data science platforms. FPGAs as accelerators for graph processing with a customizable memory hierarchy promise solving performance problems caused by inherent irregular memory access patterns on traditional hardware (e.g., CPU). However, developing such hardware accelerators is yet time-consuming and difficult and benchmarking is non-standardized, hindering comprehension of the impact of memory access pattern changes and systematic engineering of graph processing accelerators. In this work, we propose a simulation environment for the analysis of graph processing accelerators based on simulating their memory access patterns. Further, we evaluate our approach on two state-of-the-art FPGA graph processing accelerators and show reproducibility, comparablity, as well as the shortened development process by an example. Not implementing the cycle-accurate internal data flow on accelerator hardware like FPGAs significantly reduces the implementation time, increases the benchmark parameter transparency, and allows comparison of graph processing approaches. | en |
| dc.identifier.doi | 10.18420/btw2021-05 | |
| dc.identifier.isbn | 978-3-88579-705-0 | |
| dc.identifier.pissn | 1617-5468 | |
| dc.identifier.uri | https://dl.gi.de/handle/20.500.12116/35810 | |
| dc.language.iso | en | |
| dc.publisher | Gesellschaft für Informatik, Bonn | |
| dc.relation.ispartof | BTW 2021 | |
| dc.relation.ispartofseries | Lecture Notes in Informatics (LNI) - Proceedings, Volume P-311 | |
| dc.subject | DRAM | |
| dc.subject | FPGA | |
| dc.subject | Graph processing | |
| dc.subject | Irregular memory access patterns | |
| dc.subject | Simulation | |
| dc.title | Exploring Memory Access Patterns for Graph Processing Accelerators | en |
| gi.citation.endPage | 122 | |
| gi.citation.startPage | 101 | |
| gi.conference.date | 13.-17. September 2021 | |
| gi.conference.location | Dresden | |
| gi.conference.sessiontitle | Database Technology |
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