ReProVide: Towards Utilizing Heterogeneous Partially Reconfigurable Architectures for Near-Memory Data Processing
| dc.contributor.author | Becher, Andreas | |
| dc.contributor.author | Herrmann, Achim | |
| dc.contributor.author | Wildermann, Stefan | |
| dc.contributor.author | Teich, Jürgen | |
| dc.contributor.editor | Meyer, Holger | |
| dc.contributor.editor | Ritter, Norbert | |
| dc.contributor.editor | Thor, Andreas | |
| dc.contributor.editor | Nicklas, Daniela | |
| dc.contributor.editor | Heuer, Andreas | |
| dc.contributor.editor | Klettke, Meike | |
| dc.date.accessioned | 2019-04-15T11:40:40Z | |
| dc.date.available | 2019-04-15T11:40:40Z | |
| dc.date.issued | 2019 | |
| dc.description.abstract | Reconfigurable hardware such as Field-programmable Gate Arrays (FPGAs) is widely used for data processing in databases. Most of the related work focuses on accelerating one or a small set of specific operations like sort, join, regular expression matching. A drawback of such approaches is often the assumed static accelerator hardware architecture: Rather than adapting the hardware to fit the query, the query plan has to be adapted to fit the hardware. Moreover, operators or data types that are not supported by the accelerator have to be processed in software. As a remedy, approaches for exploiting the dynamic partial reconfigurability of FPGAs have been proposed that are able to adapt the datapath at runtime. However, on modern FPGAs, this introduces new challenges due to the heterogeneity of the available resources. In addition, not only the execution resources may be heterogeneous but also the memory resources. This work focuses on the architectural aspects of database (co-)processing on heterogeneous FPGA-based PSoC (programmable System-on-Chip) architectures including processors, specialized hardware components, multiple memory types and dynamically partially reconfigurable areas. We present an approach to support such (co-)processing called ReProVide. In particular, we introduce a model to formalize the challenging task of operator placement and buffer allocation onto such heterogeneous hardware and describe the difficulties of finding good placements. Furthermore, a detailed insight into different memory types and their peculiarities is given in order to use the strength of heterogeneous memory architectures. Here, we also highlight the implications of heterogeneous memories for the problem of query placement. | en |
| dc.identifier.doi | 10.18420/btw2019-ws-04 | |
| dc.identifier.isbn | 978-3-88579-684-8 | |
| dc.identifier.pissn | 1617-5468 | |
| dc.identifier.uri | https://dl.gi.de/handle/20.500.12116/21825 | |
| dc.language.iso | en | |
| dc.publisher | Gesellschaft für Informatik, Bonn | |
| dc.relation.ispartof | BTW 2019 – Workshopband | |
| dc.relation.ispartofseries | Lecture Notes in Informatics (LNI) – Proceedings, Volume P-290 | |
| dc.subject | FPGA | |
| dc.subject | Shared Memory | |
| dc.subject | Query Acceleration | |
| dc.subject | Near-Memory Processing | |
| dc.title | ReProVide: Towards Utilizing Heterogeneous Partially Reconfigurable Architectures for Near-Memory Data Processing | en |
| gi.citation.endPage | 70 | |
| gi.citation.startPage | 51 | |
| gi.conference.date | 4.-8. März 2019 | |
| gi.conference.location | Rostock | |
| gi.conference.sessiontitle | 1st Workshop on Novel Data Management Ideas on Heterogeneous (Co-)Processors (NoDMC) |
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