An Architecture Framework for Porting Applications to FPGAs
| dc.contributor.author | Nowak, Fabian | |
| dc.contributor.author | Bromberger, Michael | |
| dc.contributor.author | Karl, Wolfgang | |
| dc.date.accessioned | 2017-06-29T16:28:10Z | |
| dc.date.available | 2017-06-29T16:28:10Z | |
| dc.date.issued | 2014 | |
| dc.description.abstract | High-level language converters help creating FPGAbased accelerators and allow to rapidly come up with a working prototype. But the generated state machines do often not perform as optimal as hand-designed control units, and they require much area. Also, the created deep pipelines are not very efficient for small amounts of data. Our approach is an architecture framework of hand-coded building blocks (BBs). A microprogrammable control unit allows programming the BBs to perform computations in a data-flow style. We accelerate applications further by executing independent tasks in parallel on different BBs. Our microprogram implementation for the Conjugate-Gradient method on our data-driven, microprogrammable, task-parallel architecture framework on the Convey HC-1 is competitive with a 24-thread Intel Westmere system. It is 1.2× faster using only one out of four available FPGAs, thereby proving its potential for accelerating numerical applications. Moreover, we show that hardware developers can change the BBs and thereby reduce iteration count of a numerical algorithm like the ConjugateGradient method to less than 0.5× due to more precise operations inside the BBs, speeding up execution time 2.47×. | en |
| dc.identifier.pissn | 0177-0454 | |
| dc.language.iso | en | |
| dc.publisher | Gesellschaft für Informatik e.V., Fachgruppe PARS | |
| dc.relation.ispartof | PARS-Mitteilungen: Vol. 31, Nr. 1 | |
| dc.title | An Architecture Framework for Porting Applications to FPGAs | en |
| dc.type | Text/Journal Article | |
| gi.citation.publisherPlace | Berlin |
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