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Processor coupling architecture for aggressive voltage scaling on multicores

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dc.contributor.authorKugata, Koji
dc.contributor.authorSoda, Shinpei
dc.contributor.authorNakata, Yohei
dc.contributor.authorOkumura, Shunsuke
dc.contributor.authorIzumi, Shintaro
dc.contributor.authorYoshimoto, Masahiko
dc.contributor.authorKawaguchi, Hiroshi
dc.contributor.editorMühl, Gero
dc.contributor.editorRichling, Jan
dc.contributor.editorHerkersdorf, Andreas
dc.date.accessioned2019-10-30T12:50:18Z
dc.date.available2019-10-30T12:50:18Z
dc.date.issued2012
dc.description.abstractWe propose novel multicore architecture in which dual processors (positive-true processor element and negativetrue processor element: pPE and nPE) can be combined and serve as a low-voltage/high-performance single PE. The coupling processor occupies a double area, but it operates at a lower voltage or faster than the original processor. The proposed scheme is suitable to voltage scaling on multicores that have abundant PEs. To evaluate and demonstrate the proposed architecture, we designed octa-core coupling DSP in a 65-nm CMOS technology, on which we confirmed a 1-MHz operation at a single supply voltage of 0.5 V.en
dc.identifier.isbn978-3-88579-294-9
dc.identifier.pissn1617-5468
dc.identifier.urihttps://dl.gi.de/handle/20.500.12116/29508
dc.language.isoen
dc.publisherGesellschaft für Informatik e.V.
dc.relation.ispartofARCS 2012 Workshops
dc.relation.ispartofseriesLecture Notes in Informatics (LNI) - Proceedings, Volume P-200
dc.titleProcessor coupling architecture for aggressive voltage scaling on multicoresen
dc.typeText/Conference Paper
gi.citation.endPage384
gi.citation.publisherPlaceBonn
gi.citation.startPage375
gi.conference.date28. Februar-2. März 2012
gi.conference.locationMünchen
gi.conference.sessiontitleRegular Research Papers

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