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An architecture for runtime evaluation of soc reliability

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dc.contributor.authorBernauer, Andreas
dc.contributor.authorBringmann, Oliver
dc.contributor.authorRosenstiel, Wolfgang
dc.contributor.authorBouajila, Abdelmajid
dc.contributor.authorStechele, Walter
dc.contributor.authorHerkersdorf, Andreas
dc.contributor.editorHochberger, Christian
dc.contributor.editorLiskowsky, Rüdiger
dc.date.accessioned2019-06-12T12:32:10Z
dc.date.available2019-06-12T12:32:10Z
dc.date.issued2006
dc.description.abstractThis paper presents an architecture to evaluate the reliability of a systemon-chip (SoC) during its runtime that also accounts for the system's redundancy. We propose to integrate an autonomic layer into the SoC to detect the chip's current condition and instruct appropriate countermeasures. In the autonomic layer, error counters are used to count the number of errors within a fixed time interval. The counters' values accumulate into a global register representing the system's reliability. The accumulation takes into account the series and parallel composition of the system.en
dc.identifier.isbn978-3-88579-187-4
dc.identifier.pissn1617-5468
dc.identifier.urihttps://dl.gi.de/handle/20.500.12116/23672
dc.language.isoen
dc.publisherGesellschaft für Informatik e.V.
dc.relation.ispartofINFORMATIK 2006 – Informatik für Menschen, Band 1
dc.relation.ispartofseriesLecture Notes in Informatics (LNI) - Proceedings, Volume P-93
dc.titleAn architecture for runtime evaluation of soc reliabilityen
dc.typeText/Conference Paper
gi.citation.endPage184
gi.citation.publisherPlaceBonn
gi.citation.startPage177
gi.conference.date2.-6. Oktober 2006
gi.conference.locationDresden
gi.conference.sessiontitleRegular Research Papers

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P093 - INFORMATIK 2006 - Informatik für Menschen - Band I