Detection and correction of logic errors using extra time slots
| dc.contributor.author | Dicorato, Davide | |
| dc.contributor.author | Vierhaus, Heinrich T. | |
| dc.contributor.editor | Cunningham, Douglas W. | |
| dc.contributor.editor | Hofstedt, Petra | |
| dc.contributor.editor | Meer, Klaus | |
| dc.contributor.editor | Schmitt, Ingo | |
| dc.date.accessioned | 2017-06-30T08:14:53Z | |
| dc.date.available | 2017-06-30T08:14:53Z | |
| dc.date.issued | 2015 | |
| dc.description.abstract | Digital integrated circuits fabricated in nano-technologies have first shown to be more vulnerable to transient errors effects than their predecessors. But they also show effects of stressinduced defects resulting in early life-time failures. In general, power dissipation problems and dielectric stress, due to high field strength, are the main reasons for shortened life-time expectations. On the other hand, system designers require highly reliable and long-time dependable hardware, for example in automotive applications. On-line error detection andcompensation using either codes or, in the more general case, double or triple modular redundancy (DM R and TM R), has been used for decades, but causes higher power dissipation in nano-logic, additional stress, and is therefore no cure in terms of life-time extension. Savings on hardware and power are possible, if resources can be re-allocated to produce local TM R upon demand. However, such techniques may cause sudden signal delays after the detection of errors, which are not easy to handle in synchronous systems. In this paper we present a pseudo-TM R approach, which has little influence on timing in the “good case” and performs a regular error correction within 3 extra clock cycles under error correction without limits on the fault model . | en |
| dc.identifier.isbn | 978-3-88579-640-4 | |
| dc.identifier.pissn | 1617-5468 | |
| dc.language.iso | en | |
| dc.publisher | Gesellschaft für Informatik e.V. | |
| dc.relation.ispartof | INFORMATIK 2015 | |
| dc.relation.ispartofseries | Lecture Notes in Informatics (LNI) - Proceedings, Volume P-246 | |
| dc.title | Detection and correction of logic errors using extra time slots | en |
| dc.type | Text/Conference Paper | |
| gi.citation.endPage | 1443 | |
| gi.citation.publisherPlace | Bonn | |
| gi.citation.startPage | 1431 | |
| gi.conference.date | 28. September - 2. Oktober 2015 | |
| gi.conference.location | Cottbus |
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