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Reliability Bottlenecks in Integrated Parallel Fault-Tolerant Systems

dc.contributor.authorFechner, Bernhard
dc.date.accessioned2017-12-06T08:59:33Z
dc.date.available2017-12-06T08:59:33Z
dc.date.issued2012
dc.description.abstractBernhard Fechner, Department of Mathematics and Computer Science, Parallel Computing and VLSI Group, FernUniversität in Hagen, 58084 Hagen, Germanyen
dc.identifier.doi10.1007/BF03345458
dc.identifier.pissn0724-5319
dc.identifier.urihttps://dl.gi.de/handle/20.500.12116/8543
dc.language.isoen
dc.publisherGesellschaft für Informatik e.V.
dc.relation.ispartofFERS-Mitteilungen: Vol. 30, No. 1
dc.relation.ispartofseriesFERS-Mitteilungen
dc.subjectPhysical Layer
dc.subjectField Programmable Gate Array
dc.subjectFault Model
dc.subjectFinite State Machine
dc.subjectTransient Fault
dc.titleReliability Bottlenecks in Integrated Parallel Fault-Tolerant Systemsen
dc.typeText/Journal Article
gi.citation.endPage9
gi.citation.startPage4

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