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Design and error analysis of accuracy-configurable sequential multipliers via segmented carry chains

dc.contributor.authorEchavarria, Jorge
dc.contributor.authorWildermann, Stefan
dc.contributor.authorKeszocze, Oliver
dc.contributor.authorKhosravi, Faramarz
dc.contributor.authorBecher, Andreas
dc.contributor.authorTeich, Jürgen
dc.date.accessioned2022-11-22T09:53:17Z
dc.date.available2022-11-22T09:53:17Z
dc.date.issued2022
dc.description.abstractWe present the design and a closed-form error analysis of accuracy-configurable multipliers via segmented carry chains. To address this problem, we model the approximate partial-product accumulations as a sequential process. According to a given splitting point of the carry chains, the technique herein discussed allows varying the quality of the accumulations and, consequently, the overall product. Due to these shorter critical paths, such kinds of approximate multipliers can trade-off accuracy for an increased performance whilst exploiting the inherent area savings of sequential over combinatorial approaches. We implemented multiple architectures targeting FPGAs and ASICs with different bit-widths and accuracy configurations to 1) estimate resources, power consumption, and delay, as well as to 2) evaluate those error metrics that belong to the so-called #P-complete class.en
dc.identifier.doi10.1515/itit-2021-0040
dc.identifier.pissn2196-7032
dc.identifier.urihttps://dl.gi.de/handle/20.500.12116/39758
dc.language.isoen
dc.publisherDe Gruyter
dc.relation.ispartofit - Information Technology: Vol. 64, No. 3
dc.subjectApproximate Computing
dc.subjectSequential Multiplier
dc.subjectError Analysis
dc.titleDesign and error analysis of accuracy-configurable sequential multipliers via segmented carry chainsen
dc.typeText/Journal Article
gi.citation.endPage98
gi.citation.publisherPlaceBerlin
gi.citation.startPage89
gi.conference.sessiontitleArticle

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