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Synchronization Mechanism of Hardware and High-level Models for Performance Verification

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dc.contributor.authorCabezas, Victoria
dc.contributor.authorDöring, Andreas
dc.contributor.authorIneichen, Hanspeter
dc.date.accessioned2017-12-06T09:06:20Z
dc.date.available2017-12-06T09:06:20Z
dc.date.issued2011
dc.description.abstractVictoria Caparr´ os Cabezas1 , Andreas C. D¨ oring1 , Hanspeter Ineichen2en
dc.identifier.doi10.1007/BF03341983
dc.identifier.pissn0177-0454
dc.identifier.urihttps://dl.gi.de/handle/20.500.12116/8592
dc.language.isoen
dc.publisherGesellschaft für Informatik e.V.
dc.relation.ispartofPARS: Parallel-Algorithmen, -Rechnerstrukturen und -Systemsoftware: Vol. 28, No. 1
dc.relation.ispartofseriesPARS: Parallel-Algorithmen, -Rechnerstrukturen und -Systemsoftware
dc.subjectVirtual Channel
dc.subjectSynchronization Mechanism
dc.subjectChannel Manager
dc.subjectHardware Model
dc.subjectRemote Direct Memory Access
dc.titleSynchronization Mechanism of Hardware and High-level Models for Performance Verificationen
dc.typeText/Journal Article
gi.citation.endPage47
gi.citation.startPage38

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