Hierarchisches Top Down Chip Planning
| dc.contributor.author | Schürmann, Bernd | |
| dc.date.accessioned | 2018-02-02T02:16:33Z | |
| dc.date.available | 2018-02-02T02:16:33Z | |
| dc.date.issued | 1988 | |
| dc.identifier.uri | https://dl.gi.de/handle/20.500.12116/15687 | |
| dc.language.iso | de | |
| dc.publisher | Springer-Verlag | |
| dc.relation.ispartof | Informatik Spektrum: Vol. 11, No. 2 | |
| dc.title | Hierarchisches Top Down Chip Planning | de |
| dc.type | Text/Journal Article | |
| gi.citation.endPage | 70 | |
| gi.citation.publisherPlace | Berlin Heidelberg | |
| gi.citation.startPage | 57 |