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Correction of faulty signal transmission for resilient designs of signed-digit arithmetic

dc.contributor.authorNeuhäuser, David
dc.contributor.authorZehendner, Eberhard
dc.contributor.editorMühl, Gero
dc.contributor.editorRichling, Jan
dc.contributor.editorHerkersdorf, Andreas
dc.date.accessioned2019-10-30T12:50:12Z
dc.date.available2019-10-30T12:50:12Z
dc.date.issued2012
dc.description.abstractWhen arithmetic components are parallelized, fault-prone interconnections can tamper results significantly. Advances in feature size shrinking lead to a steady increase of errors caused by faulty transmission. We suggest to employ resilient data encoding schemes to offset these negative effects. Focusing on parallel signed-digit based arithmetic, frequently used in high-speed systems, we found that a suitable data encoding can reduce error rates by about 25% when using 2-bit encoding and about 62% when using 3-bit encoding. Data encoding should be driven by symbol occurrence probabilities. We develop a methodology to obtain these probabilities, show example fault-tolerant encodings, and discuss the impact on communicating parallel arithmetic circuits in example error scenarios.en
dc.identifier.isbn978-3-88579-294-9
dc.identifier.pissn1617-5468
dc.identifier.urihttps://dl.gi.de/handle/20.500.12116/29493
dc.language.isoen
dc.publisherGesellschaft für Informatik e.V.
dc.relation.ispartofARCS 2012 Workshops
dc.relation.ispartofseriesLecture Notes in Informatics (LNI) - Proceedings, Volume P-200
dc.titleCorrection of faulty signal transmission for resilient designs of signed-digit arithmeticen
dc.typeText/Conference Paper
gi.citation.endPage220
gi.citation.publisherPlaceBonn
gi.citation.startPage211
gi.conference.date28. Februar-2. März 2012
gi.conference.locationMünchen
gi.conference.sessiontitleRegular Research Papers

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