Generating Optimized FPGA Based MPSoCs to Parallelize Legacy Embedded Software with Customizable Throughput
| dc.contributor.author | Heid, Kris | |
| dc.contributor.author | Hochberger, Christian | |
| dc.date.accessioned | 2020-08-25T09:05:21Z | |
| dc.date.available | 2020-08-25T09:05:21Z | |
| dc.date.issued | 2020 | |
| dc.description.abstract | Executing legacy software on newly developed systems can lead to problems regarding the required throughput of the software. Automatic software parallelization can help to achieve a desired exection time even if a single core version would be to slow. In this contribution, we present a toolset that automatically parallelizes a given legacy software and distributes it to multiple soft-cores forming a processing pipeline. As a goal for the parallelization, the user can provide a minimum throughput that has to be achieved. Although this concept is limited to repetitive tasks, it can be well applied to most embedded system applications. The results show that the tool achieves remarkable speedups without any manual intervention or code restructuring for a sprectrum of benchmarks. | en |
| dc.identifier.pissn | 0177-0454 | |
| dc.identifier.uri | https://dl.gi.de/handle/20.500.12116/33867 | |
| dc.language.iso | en | |
| dc.publisher | Gesellschaft für Informatik e.V., Fachgruppe PARS | |
| dc.relation.ispartof | PARS-Mitteilungen: Vol. 35, Nr. 1 | |
| dc.title | Generating Optimized FPGA Based MPSoCs to Parallelize Legacy Embedded Software with Customizable Throughput | en |
| dc.type | Text/Journal Article | |
| gi.citation.endPage | 84 | |
| gi.citation.publisherPlace | Berlin | |
| gi.citation.startPage | 73 |
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