Synchronization of MPI One-Sided Communication on a Non-Cache-Coherent Many-Core System
| dc.contributor.author | Christgau, Steffen | |
| dc.contributor.author | Schnor, Bettina | |
| dc.date.accessioned | 2017-06-29T11:45:48Z | |
| dc.date.available | 2017-06-29T11:45:48Z | |
| dc.date.issued | 2016 | |
| dc.description.abstract | This paper discusses the design and implementation of MPI’s general active target synchronization on the Intel Single-Chip Cloud Computer, a non-cache-coherent many-core CPU. Measurements show a performance benefit of a factor of four compared to the default SCC-tuned MPI implementation and demonstrate the feasibility of implementing efficiently a shared memory protocol despite the lack of cache coherence. Further, a classification of implementation designs of MPI’s general active target synchronization is presented. | en |
| dc.identifier.pissn | 0177-0454 | |
| dc.language.iso | en | |
| dc.publisher | Gesellschaft für Informatik e.V., Fachgruppe PARS | |
| dc.relation.ispartof | PARS-Mitteilungen: Vol. 33, Nr. 1 | |
| dc.relation.ispartof | 12. PASA-Workshop 2016 | |
| dc.title | Synchronization of MPI One-Sided Communication on a Non-Cache-Coherent Many-Core System | en |
| dc.type | Text/Journal Article | |
| gi.citation.endPage | 10 | |
| gi.citation.publisherPlace | Berlin | |
| gi.citation.startPage | 5 |
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