Reconfigurable Computing Hypervisors: State-of-the-Art and Ways Ahead
| dc.contributor.author | Janson, Vincent | |
| dc.contributor.author | Nöldeke, Phillip | |
| dc.contributor.author | Kleine, Samuel | |
| dc.contributor.author | Durak, Umut | |
| dc.contributor.editor | Feichtinger, Kevin | |
| dc.contributor.editor | Sonnleithner, Lisa | |
| dc.contributor.editor | Hajiabadi, Hamideh | |
| dc.date.accessioned | 2025-02-14T10:03:36Z | |
| dc.date.available | 2025-02-14T10:03:36Z | |
| dc.date.issued | 2025 | |
| dc.description.abstract | Increasing complexity in automation and autonomy features in aircraft, particularly with the introduction of Machine Learning (ML) based approaches is leading to a growing interest in highly parallel processing architectures, Graphical Processing Units (GPUs). However, GPUs come with challenges, such as certification, weight and thermal design. Another solution is the use of Commercial of the Shelf (COTS) System on Chips (SoCs), combining traditional Processing System (PS) with a Central Processing Unit (CPU) with a tightly coupled Programming Logic (PL) consisting of a Field Programmable Gate Array (FPGA). Through the use of a hypervisor within the PS, multiple partitioned software applications can be concurrently executed on a single computing platform, even if they have distinct criticality levels, while the PL lends itself as a dedicated and configurable, highly deterministic ML accelerator. However, depending on available logic gates within the PL, the complexity of the ML algorithm itself and the number of overall ML algorithms, the PL might not have enough resources to host all required accelerators at once. A potential solution is discussed in this paper: Reconfigurable Computing (RC) Hypervisors. In this work, classical hypervisors and RC hypervisors will be examined regarding their functionalities and key differences. Further, relevant publications in this field are compared with respect to their reconfiguration mechanism and functionality. Lastly, the limitations regarding potential aviation applications, both concerning performance and safety, are discussed. Based on the discussed topic, a new RC hypervisor concept is presented. | en |
| dc.identifier.doi | 10.18420/se2025-ws-06 | |
| dc.identifier.eissn | 2944-7682 | |
| dc.identifier.issn | 2944-7682 | |
| dc.identifier.uri | https://dl.gi.de/handle/20.500.12116/45848 | |
| dc.language.iso | en | |
| dc.publisher | Gesellschaft für Informatik, Bonn | |
| dc.relation.ispartof | Software Engineering 2025 – Companion Proceedings | |
| dc.subject | Reconfigurable Hypervisor | |
| dc.subject | AI Accelerator | |
| dc.subject | System-on-Chip | |
| dc.subject | Avionic Computing | |
| dc.title | Reconfigurable Computing Hypervisors: State-of-the-Art and Ways Ahead | en |
| dc.title.subtitle | State-of-the-Art and Ways Ahead | en |
| mci.conference.date | 22.-28. Februar 2025 | |
| mci.conference.location | Karlsruhe | |
| mci.conference.sessiontitle | 7th Workshop on Avionics Systems and Software Engineering (AvioSE’25) | |
| mci.reference.pages | 53-65 |
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