Formal verification of multiplier circuits using computer algebra
| dc.contributor.author | Kaufmann, Daniela | |
| dc.date.accessioned | 2023-02-28T11:17:17Z | |
| dc.date.available | 2023-02-28T11:17:17Z | |
| dc.date.issued | 2022 | |
| dc.description.abstract | Digital circuits are widely utilized in computers, because they provide models for various digital components and arithmetic operations. Arithmetic circuits are a subclass of digital circuits that are used to execute Boolean algebra. To avoid problems like the infamous Pentium FDIV bug, it is critical to ensure that arithmetic circuits are correct. Formal verification can be used to determine the correctness of a circuit with respect to a certain specification. However, arithmetic circuits, particularly integer multipliers, represent a challenge to current verification methodologies and, in reality, still necessitate a significant amount of manual labor. In my dissertation we examine and develop automated reasoning approaches based on computer algebra, where the word-level specification, modeled as a polynomial, is reduced by a Gröbner basis inferred by the gate-level representation of the circuit. We provide a precise formalization of this reasoning process, which includes soundness and completeness arguments and adds to the mathematical background in this field. On the practical side we present an unique incremental column-wise verification algorithm and preprocessing approaches based on variable elimination that simplify the inferred Gröbner basis. Furthermore, we provide an algebraic proof calculus in this thesis that allows obtaining certificates as a by-product of circuit verification in order to boost confidence in the outcomes of automated reasoning tools. These certificates can be efficiently verified with independent proof checking tools. | en |
| dc.identifier.doi | 10.1515/itit-2022-0039 | |
| dc.identifier.pissn | 2196-7032 | |
| dc.identifier.uri | https://dl.gi.de/handle/20.500.12116/40504 | |
| dc.language.iso | en | |
| dc.publisher | De Gruyter | |
| dc.relation.ispartof | it - Information Technology: Vol. 64, No. 6 | |
| dc.subject | Applied formal methods; hardware verification; algebraic reasoning; SAT solving; proof systems | |
| dc.title | Formal verification of multiplier circuits using computer algebra | en |
| dc.type | Text/Journal Article | |
| gi.citation.endPage | 291 | |
| gi.citation.publisherPlace | Berlin | |
| gi.citation.startPage | 285 | |
| gi.conference.sessiontitle | Article |