Neuhäuser, DavidZehendner, Eberhard2017-12-062017-12-062012https://dl.gi.de/handle/20.500.12116/8617When arithmetic components are parallelized, fault-prone interconnections can tamper results significantly. Constantly progressing technology scaling leads to a steady increase of errors caused by faulty transmission. Resilient data encoding schemes can be used to offset these negative effects. Focusing on parallel signed-digit based arithmetic frequently used in high-speed systems, we propose suitable data encodings that reduce error rates by 25%. Data encoding should be driven by the occurrence probabilities of digits. We develop a methodology to obtain these probabilities, show an example fault-tolerant encoding, and discuss its impact on communicating parallel arithmetic circuits in an example error scenario.enReduce Error RateDigit ErrorDigit ProbabilityError ScenarioRedundant EncodeText/Journal Article10.1007/BF033420210177-0454