Swierzy, BenHoffmann, MelinaBoes, FelixBetke, FelixHein, LennartShevchishin, MaximSohn, Jan-NiklasMeier, MichaelWendzel, SteffenWressnegger, ChristianHartmann, LauraFreiling, FelixArmknecht, FrederikReinfelder, Lena2024-04-192024-04-192024978-3-88579-739-5https://dl.gi.de/handle/20.500.12116/43953Side channel attacks have been an active field of attacker research for decades. The Spectre, Meltdown and Load Value Injection publications established a new type of attacks, known as transient execution attacks, which utilize that architectural rollbacks leave traces in microarchitectural caches and buffers. These can serve as covert channels, resulting in practically relevant but hard to prevent attack scenarios. The associated weaknesses are complex, which makes it hard for security researchers to detect them and even harder for developers to prevent them. To achieve advancements in this field it is important to teach students about the underlying concepts. However, the documentation of modern CPUs is neither complete nor correct, which increases difficulties in obtaining practical experience. As a result, there is a need for a CPU emulator that facilitates practical learning with options for looking inside the box. We contribute TEEM, a Transient Execution EMulator of a RISC-V CPU supporting several microarchitectural features relevant for teaching transient execution attacks. Our empirical teaching experiences clearly indicate an improvement in the student’s understanding of Meltdown and Spectre.enSide Channel AttacksEmulationTeachingText/Conference Paper10.18420/sicherheit2024_0131617-5468