Septinus, K.Dragone, S.Langner, M.Blume, H.Pirsch, P.2017-12-062017-12-062011https://dl.gi.de/handle/20.500.12116/8594K. Septinus1 , S. Dragone2 , M. Langner1 , H. Blume1 , and P. Pirsch1enClock CycleExternal MemoryTime EntryMemory TransferHeap StructureA Scalable Hardware Algorithm for Demanding Timer Management in Network SystemsText/Journal Article10.1007/BF033419850177-0454