Zuber, PaulMüller, Florian HelmutStechele, WalterCremers, Armin B.Manthey, RainerMartini, PeterSteinhage, Volker2019-10-112019-10-1120053-88579-396-2https://dl.gi.de/handle/20.500.12116/28057In this work, we identify the power-optimal wire spacing as a geometric program. Its solution is a vector of individual distances between the wires. To quantify the optimization potential by this method we model the output of a grid based router with a set of parallel wires. A comparison of the power values before and after geometric optimization shows that the optimization potential lies well in the two digit percent zone for a representative circuit model in a 130nm process.enOptimization potential of CMOS power by wire spacingText/Conference Paper1617-5468