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ViCE-UPSLA: A visual high level language for accurate simulation of interlocked pipelined processors

Author:
Klassen, Dennis [DBLP]
Abstract
Simulation of processors is needed in early stages of development to reduce cost and increase quality of processor designs. Suitable simulators can be generated automatically from high-level specifications of the processor architecture. For this purpose, we have developed the domain specific visual language ViCE-UPSLA. It allows to describe pipeline based register-register, register-memory processor architectures and generates efficient simulators for such processors. In this way a variety of processors can be quickly prototyped for validation and evaluation. We have successfully used ViCE-UPSLA to model and simulate a processor with an ARM [ARM00] like architecture.
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Klassen, D., (2013). ViCE-UPSLA: A visual high level language for accurate simulation of interlocked pipelined processors. In: Wagner, S. & Lichter, H. (Hrsg.), Software Engineering 2013 - Workshopband. Bonn: Gesellschaft für Informatik e.V.. (S. 59-74).
@inproceedings{mci/Klassen2013,
author = {Klassen, Dennis},
title = {ViCE-UPSLA: A visual high level language for accurate simulation of interlocked pipelined processors},
booktitle = {Software Engineering 2013 - Workshopband},
year = {2013},
editor = {Wagner, Stefan AND Lichter, Horst} ,
pages = { 59-74 },
publisher = {Gesellschaft für Informatik e.V.},
address = {Bonn}
}
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More Info

ISBN: 978-3-88579-609-1
ISSN: 1617-5468
xmlui.MetaDataDisplay.field.date: 2013
Language: en (en)
Content Type: Text/Conference Paper
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  • P215 - Software Engineering 2013 Workshopband (inkl. Doktorandensymposium) [59]

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Gesellschaft für Informatik e.V. (GI), Kontakt: Geschäftsstelle der GI
Diese Digital Library basiert auf DSpace.