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A Scalable Hardware Algorithm for Demanding Timer Management in Network Systems

dc.contributor.authorSeptinus, K.
dc.contributor.authorDragone, S.
dc.contributor.authorLangner, M.
dc.contributor.authorBlume, H.
dc.contributor.authorPirsch, P.
dc.date.accessioned2017-12-06T09:06:20Z
dc.date.available2017-12-06T09:06:20Z
dc.date.issued2011
dc.identifier.issn0177-0454
dc.identifier.urihttp://dl.gi.de/handle/20.500.12116/8594
dc.description.abstractK. Septinus1 , S. Dragone2 , M. Langner1 , H. Blume1 , and P. Pirsch1en
dc.language.isoen
dc.publisherGesellschaft für Informatik e.V.
dc.relation.ispartofPARS: Parallel-Algorithmen, -Rechnerstrukturen und -Systemsoftware: Vol. 28, No. 1
dc.relation.ispartofseriesPARS: Parallel-Algorithmen, -Rechnerstrukturen und -Systemsoftware
dc.subjectClock Cycle
dc.subjectExternal Memory
dc.subjectTime Entry
dc.subjectMemory Transfer
dc.subjectHeap Structure
dc.titleA Scalable Hardware Algorithm for Demanding Timer Management in Network Systemsen
dc.typeText/Journal Article
mci.reference.pages58-67
dc.identifier.doi10.1007/BF03341985


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