Comparing MPI Passive Target Synchronization Schemes on a Non-Cache-Coherent Shared-Memory Processor
| dc.contributor.author | Christgau, Steffen | |
| dc.contributor.author | Schnor, Bettina | |
| dc.date.accessioned | 2020-08-25T09:05:19Z | |
| dc.date.available | 2020-08-25T09:05:19Z | |
| dc.date.issued | 2020 | |
| dc.description.abstract | MPI passive target synchronisation offers exclusive and shared locks. These are the building blocks for the implementation of applications with Readers & Writers semantic, like for example distributed hash tables. This paper discusses the implementation of MPI passive target synchronisation on a non-cache-coherent multicore, the Intel Single-Chip Cloud Computer. The considered algorithms differ in their communication style, their data structures, and their semantics. It is shown that shared memory approaches scale very well and deliver good performance, even in absence of cache coherence. | en |
| dc.identifier.pissn | 0177-0454 | |
| dc.identifier.uri | https://dl.gi.de/handle/20.500.12116/33860 | |
| dc.language.iso | en | |
| dc.publisher | Gesellschaft für Informatik e.V., Fachgruppe PARS | |
| dc.relation.ispartof | PARS-Mitteilungen: Vol. 35, Nr. 1 | |
| dc.title | Comparing MPI Passive Target Synchronization Schemes on a Non-Cache-Coherent Shared-Memory Processor | en |
| dc.type | Text/Journal Article | |
| gi.citation.endPage | 132 | |
| gi.citation.publisherPlace | Berlin | |
| gi.citation.startPage | 121 |
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