Timing-accurate simulation framework for NVM-based compute-in-memory architecture exploration
| dc.contributor.author | Rietz, Vincent | |
| dc.contributor.author | Münch, Christopher | |
| dc.contributor.author | Mayahinia, Mahta | |
| dc.contributor.author | Tahoori, Mehdi | |
| dc.date.accessioned | 2023-06-06T10:40:13Z | |
| dc.date.available | 2023-06-06T10:40:13Z | |
| dc.date.issued | 2023 | |
| dc.description.abstract | Data-intensive applications have a huge demand on processor-memory communication. To reduce the amount of data transfers and their associated latency and energy, Compute-in-Memory (CIM) architectures can be used to perform operations ranging from simple binary operations to more complex operations such as additions and matrix-vector multiplications directly within the memory. However, proper adjustments to the memory hierarchy are needed to enable the execution of CIM operations. To evaluate the trade-off between the usage of different emerging non-volatile memories for CIM and conventional computing architectures, this work extends the widely used gem5 simulation framework with an extensible timing-aware main memory CIM simulation capability. This framework is used to analyze the performance of CIM extended main memory with various emerging memory technologies, namely Spin-Transfer-Torque Magnetic Random Access Memory (STT-MRAM), Redox-based RAM (ReRAM) and Phase-Change Memory (PCM). We evaluate different workloads from the PolyBench/C benchmark suite and other selected examples. In comparison to a processor-centric system, the results show a significant reduction in execution time for the majority of applications. | en |
| dc.identifier.doi | 10.1515/itit-2023-0019 | |
| dc.identifier.pissn | 2196-7032 | |
| dc.identifier.uri | https://dl.gi.de/handle/20.500.12116/41702 | |
| dc.language.iso | en | |
| dc.publisher | De Gruyter | |
| dc.relation.ispartof | it - Information Technology: Vol. 65, No. 1-2 | |
| dc.subject | architecture-level simulator; compute-in-memory (CiM); gem5; non-volatile memory | |
| dc.title | Timing-accurate simulation framework for NVM-based compute-in-memory architecture exploration | en |
| dc.type | Text/Journal Article | |
| gi.citation.endPage | 29 | |
| gi.citation.publisherPlace | Berlin | |
| gi.citation.startPage | 13 | |
| gi.conference.sessiontitle | Article |