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Formal Semantics of Synchronous Transfer Architecture

dc.contributor.authorCichon, Gordon
dc.contributor.authorHofmann, Martin
dc.contributor.editorFill, Hans-Georg
dc.contributor.editorKaragiannis, Dimitris
dc.contributor.editorReimer, Ulrich
dc.date.accessioned2019-03-19T14:06:56Z
dc.date.available2019-03-19T14:06:56Z
dc.date.issued2014
dc.description.abstractThis paper explores the use of formal verification methods for complex and highly parallel state machines. For this purpose, a framework named Synchronous Transfer Architecture (STA) is being used. STA is a generic framework for digital hardware development that contains VLIW, FPGA, and hardwired ASIC architectures as corner cases. It maintains a strictly deterministic system behavior in order to achieve substantial savings in hardware costs, thus enabling systems with high clock speed, low power consumption and small die area. The high degree of parallelism requires a diligent development methodology to avoid implementation errors. Consequently, formal verification is the methodology of choice for reliable verification. The contribution of this paper is a formal semantics for the STA hardware architecture framework. This semantics is then used for the formal verification of an optimized parallel implementation of Fast Fourier Transformation (FFT) on STA. This is achieved using a combination of the semantics and symbolic evaluation.en
dc.identifier.isbn978-388579-619-0
dc.identifier.pissn1617-5468
dc.identifier.urihttps://dl.gi.de/handle/20.500.12116/20944
dc.language.isoen
dc.publisherGesellschaft für Informatik e.V.
dc.relation.ispartofModellierung 2014
dc.relation.ispartofseriesLecture Notes in Informatics (LNI) - Proceedings, Volume P-225
dc.titleFormal Semantics of Synchronous Transfer Architectureen
dc.typeText/Conference Paper
gi.citation.endPage272
gi.citation.publisherPlaceBonn
gi.citation.startPage257
gi.conference.date19.-21. März 2014
gi.conference.locationWien, Österreich
gi.conference.sessiontitleRegular Research Papers

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