Hybrid Parallel Sort on the Cell Processor

Sorting large data sets has always been an important application, and hence has been one of the benchmark applications on new parallel architectures. We present a parallel sorting algorithm for the Cell processor that combines elements of bitonic sort and merge sort, and reduces the bandwidth to main memory by pipelining. We present runtime results of a partial prototype implementation and simulation results for the complete sorting algorithm, that promise performance advantages over previ- ous implementations.

Keller, Jörg; Kessler, Christoph; König, Kalle; Heenes, Wolfgang (2008): Hybrid Parallel Sort on the Cell Processor. 9th workshop on parallel systems and algorithms – workshop of the GI/ITG special interest groups PARS and PARVA. Bonn: Gesellschaft für Informatik e. V.. PISSN: 1617-5468. ISBN: 978-3-88579-218-5. pp. 107-112. Regular Research Papers. Dresden. February 26th, 2008

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Parallel Sort , Merge Sort , Cell Processor , Hybrid Sort

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P124 - 9th Workshop on Parallel Systems and Algorythms

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Hybrid Parallel Sort on the Cell Processor

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