Design of MPI Passive Target Synchronization for a Non-Cache-Coherent Many-Core Processor
| dc.contributor.author | Christgau, Steffen | |
| dc.contributor.author | Schnor, Bettina | |
| dc.date.accessioned | 2020-03-11T00:06:22Z | |
| dc.date.available | 2020-03-11T00:06:22Z | |
| dc.date.issued | 2017 | |
| dc.description.abstract | Distributed hash tables are a common approach for fast data access. For this kind of application, a synchronization scheme with Readers and Writers semantic is well suited. This paper presents the design of an implementation of MPI passive target synchronization with Readers and Writers semantic. The implementation is discussed for the Single-Chip Cloud Computer, a non-cachecoherent many-core CPU with shared memory. | en |
| dc.identifier.pissn | 0177-0454 | |
| dc.identifier.uri | https://dl.gi.de/handle/20.500.12116/31941 | |
| dc.language.iso | en | |
| dc.publisher | Gesellschaft für Informatik e.V., Fachgruppe PARS | |
| dc.relation.ispartof | PARS-Mitteilungen: Vol. 34, Nr. 1 | |
| dc.title | Design of MPI Passive Target Synchronization for a Non-Cache-Coherent Many-Core Processor | en |
| dc.type | Text/Journal Article | |
| gi.citation.endPage | 53 | |
| gi.citation.publisherPlace | Berlin | |
| gi.citation.startPage | 43 |
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